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plls with integrated vco - smt 1 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz functional diagram features ? rf bandwidth: 25 - 6000 mhz ? maximum phase detector rate 100 mhz ? ultra low phase noise -110 dbc/hz in band typ. ? figure of merit (fom) -227 dbc/hz ? <180 fs rms jitter ? 24-bit step size, resolution 3 hz typ ? exact frequency mode ? built in digital self test ? 40 lead 6x6 mm smt package: 36 mm 2 typical applications ? cellular infrastructure ? microwave radio ? wimax, wifi ? communications test equipment ? catv equipment ? dds replacement ? military ? tunable reference source for spurious- free performance for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 2 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz general description the HMC833LP6GE is a low noise, wide band, fractional-n phase-locked-loop (pll) that features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 1500 mhz - 3000 mhz, and an integrated vco output divider (divide by 1/2/4/6.../60/62) and doubler, that together allow the HMC833LP6GE to generate frequencies from 25 mhz to 6000 mhz. the integrated phase detector (pd) and delta-sigma modulator, capable of operating at up to 100 mhz, permit wider loop-bandwidths with excellent spectral performance. the HMC833LP6GE features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. the superior noise foor (< -170 dbc/hz) makes the HMC833LP6GE an ideal source for a variety of applications - such as; lo for rf mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications. additional features of the HMC833LP6GE include rf output power control from 0 to 9 db (3 db steps), output mute function, and a delta-sigma modulator exact frequency mode which enables users to generate output frequencies with 0 hz frequency error. parameter condition min. typ. max. units rf output characteristics output frequency 25 6000 mhz vco frequency at pll input 1500 3000 mhz rf output frequency at f vco 1500 3000 mhz output power rf output power at f fundamental = 2000 mhz across all frequencies see figure 9 broadband matched internally using gain control setting 01 [1] -3 -2 -1 dbm output power control range [2] 3 9 db output power control step [2] 1 3 db rf output power at f doubler = 3000 mhz across all frequencies see figure 9 broadband matched internally [1] -3.5 -2.5 -1.5 dbm rf output power at f doubler = 6000 mhz across all frequencies see figure 9 broadband matched internally [1] -11 -7 -5 dbm harmonics for fundamental mode fo mode at 2 ghz 2nd / 3rd / 4th -20/-29/-45 dbc fo/2 mode at 2ghz/2 = 1 ghz 2nd / 3rd / 4th -23/-15/-35 dbc fo/30 mode at 3 ghz/30 = 100 mhz 2nd / 3rd / 4th -25/-10/-33 dbc fo/62 mode at 1550 mhz/62 = 25 mhz 2nd / 3rd / 4th -17/-8/-21 dbc harmonics in doubler mode 2fo mode at 4 ghz ? / 3rd / 4th/5th -7/-23/-15/-40 dbc vco output divider vco rf divider range 1,2,4,6,8,...,62 1 62 electrical specifcations vppcp, vddls, vcc1, vcc2 = 5 v; rvdd, avdd, dvdd3v, vccpd, vcchf, vccps = 3.3 v min and max specifed across temp -40 c to 85 c [1] measured single-ended. additional 3 db possible with differential outputs. [2] output power control gain is compressed in higher frequency range (i.e. > 3 ghz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 3 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz parameter condition min. typ. max. units pll rf divider characteristics 19-bit n-divider range (integer) max = 2 19 - 1 16 524,287 19-bit n-divider range (fractional) fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 ref input characteristics max ref input frequency 350 mhz ref input voltage ac coupled [3] 1 2 3.3 vp-p ref input capacitance 5 pf 14-bit r-divider range 1 16,383 phase detector (pd) [4] pd frequency fractional mode b [5] dc 100 mhz pd frequency fractional mode a (and regis - ter 6 [17:16] = 11) dc 80 mhz pd frequency integer mode dc 125 mhz charge pump output current 0.02 2.54 ma charge pump gain step size 20 a pd/charge pump ssb phase noise 50 mhz ref, input referred 1 khz -143 dbc/hz 10 khz add 1 db for fractional -150 dbc/hz 100 khz add 3 db for fractional -153 dbc/hz logic inputs vsw 40 50 60 % dvdd logic outputs voh output high voltage dvdd v vol output low voltage 0 v output impedance 100 200 maximum load current 1.5 ma power supply voltages 3.3 v supplies avdd, vcchf, vccps, vccpd, rvdd,dvdd 3.0 3.3 3.5 v 5 v supplies vppcp, vddls, vcc1, vcc2 4.8 5 5.2 v power supply currents +5 v analog charge pump vppcp, vddcp 8 ma +5 v vco core and vco buffer fo/1 mode vcc2 105 ma fo/n mode vcc2 80 ma +5 v vco divider and rf/pll buffer fo/1 mode vcc1 25 ma fo/n mode vcc1 80 100 ma electrical specifcations (continued) [3] measured with 100 external termination. see reference input stage section for more details. [4] slew rate of greater or equal to 0.5 ns/v is recommended, see reference input stage section for more details. frequency is guaranteed across process voltage and temperature from -40 c to 85 c. [5] this maximum phase detector frequency can only be achieved if the minimum n value is respected. eg. in the case of fractional b mode, the maximum pfd rate = fvco/20 or 100 mhz, whichever is less. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 4 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz electrical specifcations (continued) parameter condition min. typ. max. units +3.3 v avdd, vcchf, vccps, vccpd, rvdd, dvdd3v 52 ma power down - crystal off reg 01h=0, crystal not clocked 10 a power down - crystal on, 100 mhz reg 01h=0, crystal clocked 100 mhz 5 ma power on reset typical reset voltage on dvdd 700 mv min dvdd voltage for no reset 1.5 v power on reset delay 250 s vco open loop phase noise at fo @ 2 ghz 10 khz offset -86 dbc/hz 100 khz offset -116 dbc/hz 1 mhz offset -141 dbc/hz 10 mhz offset -162 dbc/hz 100 mhz offset -171 dbc/hz vco open loop phase noise at fo @ 2 ghz/2 = 1 ghz 10 khz offset -92 dbc/hz 100 khz offset -122 dbc/hz 1 mhz offset -147 dbc/hz 10 mhz offset -165 dbc/hz 100 mhz offset -165 dbc/hz vco open loop phase noise at fo @3 ghz/30 = 100 mhz 10 khz offset -112 dbc/hz 100 khz offset -142 dbc/hz 1 mhz offset -165 dbc/hz 10 mhz offset -168 dbc/hz 100 mhz offset -171 dbc/hz vco open loop phase noise at 2fo @ 4 ghz 10 khz offset -80 dbc/hz 100 khz offset -110 dbc/hz 1 mhz offset -135 dbc/hz 10 mhz offset -155 dbc/hz 100 mhz offset -162 dbc/hz vco open loop phase noise at 2fo @ 6 ghz 10 khz offset -75 dbc/hz 100 khz offset -105 dbc/hz 1 mhz offset -131 dbc/hz 10 mhz offset -152 dbc/hz 100 mhz offset -162 dbc/hz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 5 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz parameter condition min. typ. max. units figure of merit floor integer mode normalized to 1 hz -230 dbc/hz floor fractional mode normalized to 1 hz -227 dbc/hz flicker (both modes) normalized to 1 hz -268 dbc/hz vco characteristics vco tuning sensitivity at 2800 mhz measured at 2.5 v 13.3 mhz/v vco tuning sensitivity at 2400 mhz measured at 2.5 v 13.8 mhz/v vco tuning sensitivity at 2000 mhz measured at 2.5 v 13.6 mhz/v vco tuning sensitivity at 1600 mhz measured at 2.5 v 12.1 mhz/v vco supply pushing measured at 2.5 v 2 mhz/v electrical specifcations (continued) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 6 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz figure 1. typical closed loop integer phase noise [loop filter confguration table] figure 2. typical closed loop fractional phase noise [loop filter confguration table] figure 3. free running phase noise figure 4. free running vco phase noise vs. temperature figure 5. typical vco sensitivity at fo -220 -200 -180 -160 -140 -120 -100 -80 1 10 100 1000 10000 100000 fout 3800 mhz,lopp bw 74khz,rms jitter 108fsec fout 3800mhz,loop filter 90khz,rms jitter 87fsec fout 5600mhz,loop bw 74khz,rms jitter 188fsec fout 1600mhz,loop bw 74khz,rms jitter 127fsec fout 1600mhz,loop bw 90khz, rms jitter 97fsec fout 5600mhz,loop bw 90khz,rms jitter 118fsec offset(khz) phase noise(dbc/hz) -220 -200 -180 -160 -140 -120 -100 -80 1 10 100 1000 10000 100000 fout 3805 mhz,loop bw 74khz,rms jitter 123fsec fout 3805mhz,loop bw 90khz,rms jitter 104fsec fout 5605mhz,loop bw 74khz,rms jitter 202fsec fout 5605mhz,loop bw 90khz,rms jitter 128fsec fout 1605mhz, loop bw 74khz,rms jitter 130fsec fout 1605mhz, loop bw 90khz, rms jitter 123fsec offset (khz) phase noise (dbc) -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 5536 mhz 4732 mhz 3885 mhz 3058 mhz phase noise (dbc/hz) offset (hz) -180 -170 -160 -150 -140 -130 -120 -110 -100 10 100 1000 10000 27c -40c 85c phase noise (dbc/hz) frequency (mhz) 100 mhz offset 1 mhz offset 100 khz offset 0 1 2 3 4 5 tune voltage after calibration (v) vco frequency(mhz) fmin fmax 1500 3000 0 10 20 30 40 50 60 012345 2817 mhz at 2.5v, tuning cap 15 2418 mhz at 2.5v, tuning cap 15 1996 mhz at 2.5v, tuning cap 15 1575 mhz at 2.5v, tuning cap 15 tuning voltage (v) kvco (mhz/v) typical performance characteristics figure 6. typical tuning voltage after calibration at fo for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 7 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz figure 7. integrated rms jitter [1] [1] rms jitter data is measured in fractional mode with 100 khz loop bandwidth using 50 mhz reference frequency from 1 khz to 20 mhz integration bandwidth. [2] the output power from frequency 25mhz to 3000mhz is using fundamental confguration with gain setting 01, output power from frequency 3000mhz to 6000mhz is using doubler confguration with gain setting 11 [3] measured from a 50 source with a 100 external resistor termination. see reference input stage section for more details. full fom performance up to maximum 3.3 vpp input voltage. figure 8. figure of merit figure 9. typical output power vs. temperature, maximum gain [2] figure 10. output power vs gain control setting figure 11. reference input sensitivity, square wave, 50 [3] figure 12. reference input sensitivity sinusoidal wave, 50 [3] 50 100 150 200 250 300 10 100 1000 10000 -40c 27c 85c jitter (fs) output frequency (mhz) -240 -230 -220 -210 -200 10 2 10 3 10 4 10 5 10 6 normalized phase noise (dbc/hz) frequency offset (hz) fom floor fom 1/f noise typ fom vs offset -12 -10 -8 -6 -4 -2 0 2 0 1000 2000 3000 4000 5000 6000 27 c -40 c 85 c output power (dbm) output frequency (mhz) 220 222 224 226 228 230 232 234 -15 -12 -9 -6 -3 0 3 14 mhz square wave 25 mhz square wave 50 mhz square wave 100 mhz square wave fom reference power (dbm) 200 205 210 215 220 225 230 235 -20 -15 -10 -5 0 5 14 mhz sin 25 mhz sin 50 mhz sin 100 mhz sin reference power (dbm) fom (dbc/hz) -10 -5 0 5 10 0 1000 2000 3000 4000 5000 6000 gain setting 11 gain setting 10 gain setting 01 gain setting 00 output power (dbm) output frequency (mhz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 8 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz figure 13. integer boundary spur at 5900.8 mhz [4] figure 14. integer boundary spur at 3800.4 mhz [5] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) [4] fractional mode b, 50 mhz pd frequency, 74 khz loop filter bw [5] fractional mode b, 50 mhz pd frequency, 74 khz loop filter bw integer boundary at 3800 mhz [6] exact frequency mode, ref in = 100 mhz, pd = 50 mhz, output divider 1 selected, loop filter bandwidth = 100 khz, channel spacing = 100 khz [7] exact frequency mode, channel spacing = 100 khz, fractional mode b rf out = 2591 mhz, ref in = 100 mhz, pd frequency = 50 mhz, output divider 1 selected, loop filter bandwidth = 120 khz, [8] fractional mode b rf out = 2591 mhz, ref in = 100 mhz, pd frequency = 50 mhz, output divider 1 selected, loop filter bandwidth = 120 khz. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) figure 15. fractional-n exact frequency mode on performance at 2113.5 mhz [6] figure 16. fractional-n exact frequency mode on performance at 2591 mhz [7] figure 17. fractional-n exact frequency mode off performance at 2591 mhz [8] -180 -160 -140 -120 -100 -80 -60 1000 10000 100000 1000000 10000000 100000000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) figure 18. rf output return loss -35 -30 -25 -20 -15 -10 -5 0 25 100 1000 10000 return loss (db) frequency (mhz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 9 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz figure 19. worst spur, fixed 50 mhz reference, output freq. = 2000.1 mhz [9] figure 20. worst spur, tunable reference, output frequency = 2000.1 mhz [10] [9] standard hmc830lp6ge integer boundary spur plot with fx pfd at 50 mhz [10] capability of hmc830lp6ge to generate low frequencies (as low as 25 mhz), enables the hmc830lp6ge to be used as a tunable reference source into the HMC833LP6GE, which maximizes spur performance of the HMC833LP6GE. please see HMC833LP6GE application information for more information. [11] the graph is generated by observing, and plotting, the magnitude of only the worst spur (largest magnitude), at any offset, at each output frequency, while using a fxed 50 mhz reference and a tunable reference tuned to 47.5 mhz. see HMC833LP6GE application information for more details. [12] phase noise performance of the HMC833LP6GE when used as a tunable reference source. HMC833LP6GE is operating at 6 ghz/30, 6 ghz/54 for the 100 mhz, 55.55 mhz curves respectively. figure 21. low frequency performance [12] -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) figure 22. low frequency performance [12] -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000khz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 10 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz loop filter bw (khz) c1 (pf) c2 (nf) c3 (pf) c4 (pf) r2 (k) r3 (k) r4 (k) loop filter design 74 150 27 220 220 0.82 1 1 90 270 3.9 56 56 1.2 1 1 214 56 1.8 na na 2.2 0 0 loop filter confguration table pin descriptions pin number function description 1 avdd dc power supply for analog circuitry. 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 29, 34, 37, 38 n/c the pins are not connected internally; however, all data shown herein was measured with these pins connected to rf/dc ground externally. 3 vppcp power supply for charge pump analog section 4 cp charge pump output 7 vddls power supply for the charge pump digital section 10 rvdd reference supply 15 xrefp reference oscillator input 16 dvdd3v dc power supply for digital (cmos) circuitry 17 cen chip enable. connect to logic high for normal operation. 23 vtune vco varactor. tuning port input. 25 vcc2 vco analog supply 2 27 vcc1 vco analog supply 1 28 rf_n rf output 30 sen pll serial port enable (cmos) logic input 31 sdi pll serial port data (cmos) logic input 32 sck pll serial port clock (cmos) logic input 33 ld_sdo lock detect, or serial data, or general purpose (cmos) logic output (gpo) 35 vcchf dc power supply for analog circuitry 36 vccps dc power supply for analog prescaler 39 vccpd dc power supply for phase detector 40 bias external bypass decoupling for precision bias circuits. note: 1.920v 20mv reference voltage (bias) is generated internally and cannot drive an external load. must be measured with 10g meter such as agilent 34410a, normal 10m dvm will read erroneously. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 11 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz outline drawing part number package body material lead finish msl rating package marking [1] HMC833LP6GE rohs-compliant low stress injection molded plastic 100% matte sn msl1 h833 xxxx [1] 4-digit lot number xxxx package information notes: 1. package body material: low stress injection molded plastic silica and silicon impregnated. 2. lead and ground paddle material: copper alloy. 3. lead and ground paddle plating: 100% matte tin. 4. dimensions are in inches [millimeters]. 5. lead spacing tolerance is non-cumulative. 6. pad burr length shall be 0.15mm max. pad burr height shall be 0.25mm max. 7. package warp shall not exceed 0.05mm. 8. all ground leads and ground paddle must be soldered to pcb rf ground. 9. refer to hittite application note for suggested pcb land pattern. absolute maximum ratings avdd, rvdd, dvdd3v, vccpd, vcchf, vccps -0.3v to +3.6v vppcp, vddls, vcc1,vcc2 -0.3v to +5.5v operating temperature -40 c to +85c storage temperature -65 c to 150c maximum junction temperature 125 c thermal resistance (r th ) (junction to ground paddle) 20 c/w refow soldering peak temperature 260c time at peak temperature 40 sec esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 12 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz evaluation pcb schematic the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. to view this evaluation pcb schematic please visit www.hittite.com and choose HMC833LP6GE from the search by part number pull down menu to view the product splash page. evaluation pcb item contents part number evaluation kit HMC833LP6GE evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software, hittite pll design software) ekit01-HMC833LP6GE evaluation order information for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 13 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz HMC833LP6GE application information large bandwidth (25 mhz to 6000 mhz), industry leading phase noise and spurious performance, excellent noise foor (<-170 dbc/hz), coupled with a high level of integration make the HMC833LP6GE ideal for a variety of applications; as an rf or if stage lo, a clock source for high-frequency data-converters, or a tunable reference source for extremely low spurious applications (< -100 dbc/hz spurs). figure 27. HMC833LP6GE in a typical transmit chain figure 28. HMC833LP6GE in a typical receive chain figure 29. hmc830lp6ge used as a tunable reference for HMC833LP6GE using the HMC833LP6GE with a tunable reference as shown in figure 25 , it is possible to drastically improve spurious emissions performance across all frequencies. example shown in figure 20 graph shows that it is possible to have spurious emissions < -100 dbc/hz across all frequencies. for more information about spurious emissions, how they are related to the reference frequency, and how to tune the reference frequency for optimal spurious performance please see the fractional operation and spurious section of this data sheet. note that at very low output frequencies < 100 mhz, harmonics increase due to small internal ac coupling. applications which are sensitive to harmonics may require external low pass fltering. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 14 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz output gain setting for optimal power flatness the output of the HMC833LP6GE is matched to 50 across all output frequencies from 25 mhz to 6000 mhz. as a result of the wideband 50 match, the output power of the HMC833LP6GE decreases with increasing output frequency, as shown in figure 9 . if required, it is possible to adjust the output stage gain setting of the HMC833LP6GE ( vco_reg 02h [7:6]) at various operating frequencies in order to achieve a more constant output power level across the frequency operating range of the HMC833LP6GE. an example is shown in figure 26 . figure 30. -20 -15 -10 -5 0 5 0 1000 2000 3000 4000 5000 6000 output power (dbm) output frequency (mhz) gain = 0 db gain = 9 db gain = 6 db divider output stage gain = 3 db (vco_reg02h[8] = 1) reducing the output power variation of HMC833LP6GE across frequency by adjusting output stage gain control. if a higher output power than that shown in figure 26 is required, it is possible to follow the HMC833LP6GE output stage with a simple amplifer such as h m c 311sc70 e in order to achieve a constant and high output power level across the entire operating range of the HMC833LP6GE. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 15 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.0 theory of operation HMC833LP6GE is targeted for ultra low phase noise applications and has been designed with very low noise reference path, phase detector and charge pump. the HMC833LP6GE consists of the following functional blocks: 1. reference path input buffers and r divider 2. vco path input buffer and multi-modulus n divider 3. ? fractional modulator 4. phase detector 5. charge pump 6. serial port with read write capability 7. general purpose output (gpo) port 8. power on reset circuit 9. vco subsystem 10. built-in self test features 1.1 vco subsystem the HMC833LP6GE contains a vco subsystem that can be confgured to operate in: ? fundamental frequency (fo) mode (1500 mhz to 3000 mhz). ? divide by n (fo/n), where n = 1,2,4,6,8...58,60,62 mode (25 mhz to 1500 mhz). ? doubler (2fo) mode (3000 mhz to 6000 mhz). all modes are vco register programmable as shown in figure 27 . one loop flter design can be used for the entire frequency of operation of the HMC833LP6GE. figure 31. pll and vco subsystems for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 16 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.2 vco calibration 1.2.1 vco auto-calibration (autocal) HMC833LP6GE uses a step tuned type vco. a simplifed step tuned vco is shown in figure 28 . a step tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequency of the vco to be adjusted or stepped by switching in/out vco tank capacitors. a more detailed view of a typical vco subsystem confguration is shown in figure 29 . a step tuned vco allows the user to center the vco on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the HMC833LP6GEs charge pump. this enables the pll charge pump to tune the vco over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). the vco switches are normally controlled automatically by the HMC833LP6GE using the auto-calibration feature. the auto-calibration feature is implemented in the internal state machine. it manages the selection of the vco sub-band (capacitor selection) when a new frequency is programmed. the vco switches may also be controlled directly via register reg 05h for testing or for other special purpose operation. other control bits specifc to the vco are also sent via reg 05h . figure 32. simplifed step tuned vco figure 33. HMC833LP6GE pll and vco subsystems to use a step tuned vco in a closed loop, the vco must be calibrated such that the HMC833LP6GE knows which switch position on the vco is optimum for the desired output frequency. the HMC833LP6GE supports auto-calibration (autocal) of the step tuned vco. the autocal fxes the vco tuning voltage at the optimum mid-point of the charge pump output, then measures the free running vco frequency while searching for the setting which results in the free running output frequency that is closest to the for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 17 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz desired phase locked frequency. this procedure results in a phase locked oscillator that locks over a very narrow voltage range on the varactor. a typical tuning curve for a step tuned vco is shown in figure 30 . note how the tuning voltage stays in a narrow range over a wide range of output frequencies. 0 1 2 3 4 5 920 960 1000 1040 1080 1120 1160 calibration frequency (mhz) tune voltage after calibration (v) 50mhz pfd, 500khz tuning steps, +25c 256 count calibration ,195khz resolution 31usec total cal time 0 15 31 figure 34. a typical 5-bit 32 switch vco tuning voltage after calibration the calibration is normally run automatically once for every change of frequency. this ensures optimum selection of vco switch settings vs. time and temperature. the user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the autocal routine. the accuracy required in the calibration affects the amount of time required to tune the vco. the calibration routine searches for the best step setting that locks the vco at the current programmed frequency, and ensures that the vco will stay locked and perform well over its full temperature range without additional calibration, regardless of the temperature that the vco was calibrated at. auto-calibration can also be disabled allowing manual vco tuning. refer to section 1.2.2 for a description of manual tuning 1.2.1.1 autocal use of reg05h autocal transfers switch control data to the vco subsystem via reg 05h . the address of the vco subsystem in reg 05h is not altered by the autocal routine. the address and id of the vco subsystem in reg 05h must be set to the correct value before autocal is executed. for more information see section 1.19 . 1.2.1.2 auto-relock on lock detect failure it is possible by setting reg 07h [13] to have the vco subsystem automatically re-run the calibration routine and re-lock itself if lock detect indicates an unlocked condition for any reason. with this option the system will attempt to re-lock only once. auto-relock is recommended. 1.2.2 manual vco calibration for fast frequency hopping if it is desirable to switch frequencies very quickly it is possible to eliminate the autocal time by calibrating the vco in advance and storing the switch number vs frequency information in the host. this can be done by initially locking the pll with integrated vco on each desired frequency using autocal, then reading, and storing the vco switch settings selected. the vco switch settings are available in reg 10h [7:0] after every autocal operation. the host must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers when autocal is disabled. hence frequency changes with manual control and autocal disabled, requires a minimum of two serial port transfers to the pll, once to set the vco switches, and once to set the pll frequency. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 18 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz if autocal is disabled reg 0ah [11]=1 , the vco will update its registers with the value written via reg 05h immediately. the vco internal transfer requires 16 vsck clock cycles after the completion of a write to reg 05h . vsck and the autocal controller clock are equal to the input reference divided by 0, 4,16 or 32 as controlled by reg 0ah [14:13] . 1.2.2.1 registers required for frequency changes in fractional mode a large change of frequency, in fractional mode ( reg 06h [11]=1 ), may require main serial port writes to: 1. the integer register intg, reg 03h (only required if the integer part changes) 2. the vco spi register, reg 05h ? required for manual control of vco if reg 0ah [11]=1 (autocal disabled) ? required to change the rf divider value if needed ( vco_reg 02h ) ? required to turn on/off the doubler mode if needed ( vco_reg 03h [0]) 3. the fractional register, reg 04h . the fractional register write triggers autocal if reg 0ah [11]= 0 , and is loaded into the modulator automatically after autocal runs. if autocal is disabled, reg 0ah [11]=1 , the fractional frequency change is loaded into the modulator immediately when the register is written with no adjustment to the vco. small steps in frequency in fractional mode, with autocal enabled ( reg 0ah [11]= 0 ), usually only require a single write to the fractional register. worst case, 5 main serial port transfers to the HMC833LP6GE could be required to change frequencies in fractional mode. if the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. in all cases, in fractional mode, it is necessary to write to the fractional register reg 04h for frequency changes. 1.2.2.2 registers required for frequency changes in integer mode a change of frequency, in integer mode ( reg 06h [11]= 0) , requires main serial port writes to: 1. vco spi register, reg 05h ? required for manual control of vco if reg 0ah [11]=1 (autocal disabled) ? required to change the rf divider value if needed ( vco_reg 02h ) ? required to turn on/off the doubler mode if needed ( vco_reg 03h [0]) 2. the integer register reg 03h . ? in integer mode, an integer register write triggers autocal if reg 0ah [11]= 0 , and is loaded into the prescaler automatically after autocal runs. if autocal is disabled, reg 0ah [11]=1 , the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the vco. normally changes to the integer register cause large steps in the vco frequency, hence the vco switch settings must be adjusted. autocal enabled is the recommended method for integer mode frequency changes. if autocal is disabled ( reg 0ah [11]=1 ), a priori knowledge of the correct vco switch setting and the corresponding adjustment to the vco is required before executing the integer frequency change. 1.2.3 vco autocal on frequency change assuming reg 0ah [11]= 0 , the vco calibration starts automatically whenever a frequency change is requested. if it is desired to rerun the autocal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the autocal routine will execute again without changing fnal frequency. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 19 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.2.4 vco autocal time & accuracy the vco frequency is counted for t mmt , the period of a single autocal measurement cycle. t mmt = t xtal r 2 n (eq 1) n is set by reg 0ah [2:0] and results in measurement periods which are multiples of the pd period, t xtal r . r is the reference path division ratio currently in use, reg 02h t xtal is the period of the external reference (crystal) oscillator. the vco autocal counter will, on average, expect to register n counts, rounded down (foor) to the nearest integer, every pd cycle. n is the ratio of the target vco frequency, f vco , to the frequency of the pd, f pd , where n can be any rational number supported by the n divider. n is set by the integer ( n int = reg 03h ) and fractional ( n frac = reg 04h ) register contents n = n int + n frac / 2 24 (eq 2) the autocal state machine and the data transfers to the internal vco subsystem spi (vspi) run at the rate of the fsm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. t fsm = t xtal 2 m (eq 3) m is 0, 2, 4 or 5 as determined by reg 0ah [14:13] the expected number of vco counts, v, is given by v = foor (n 2 n ) (eq 4) the nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r) (eq 5) where the worst case measurement error, f err , is: f err f pd / 2 n + 1 (eq 6) figure 35. vco calibration a 5-bit step tuned vco, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 vspi data transfers of 20 clock cycles each. the measurement has a programmable number of wait states, k, of 100 fsm cycles defned by reg 0ah [7:6] = k. hence total calibration time, worst case, is given by: t cal = k100t fsm + 6t pd 2 n + 7 20t fsm (eq 7) or equivalently for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 20 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz t cal = t xtal (6r 2 n + (140+100k) 2 m ) where k = reg 0ah [7:6] decimal (eq 8) for guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8 th the frequency step caused by a vco sub-band switch change. better resolution settings will show no improvement. 1.2.4.1 vco autocal example the vco subsystem must satisfy the maximum f pd limited by the two following conditions: a. n 16 (f int ), n 20.0 (f frac ), where n = f vco/ f pd b. f pd 100 mhz suppose the vco subsystem output frequency is to operate at 2.01 ghz. our example crystal frequency is f xtal = 50 mhz, r=1, and m=0 ( figure 31 ) , hence t fsm = 20 ns (50 mhz). note, when using autocal, the maximum autocal finite state machine (fsm) clock cannot exceed 60 mhz (see reg 0ah [14:13] ). the fsm clock does not affect the accuracy of the measurement, it only affects the time to produce the result. this same clock is used to clock the 16 bit vco serial port. if time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. using an input crystal of 50 mhz (r=1 and fpd=50 mhz) the times and accuracies for calibration using (eq 6) and (eq 8) are shown in table 1 . where minimal tuning time is 1/8 th of the vco band spacing. across all vcos, a measurement resolution better than 800 khz will produce correct results. setting m = 0, n = 5, provides 781 khz of resolution and adds 8.6 s of autocal time to a normal frequency hop. once the autocal sets the fnal switch value, 8.64 s after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. hence we can see in this example that autocal typically adds about 8.6 s to the normal time to achieve frequ- ency lock. hence, autocal should be used for all but the most extreme frequency hopping requirements. table 1. autocal example with f xtal = 50 mhz, r = 1, m = 0 control value reg0ah[2:0] n 2 n t mmt (s) t cal (s) f err max 0 0 1 0.02 4.92 25 mhz 1 1 2 0.04 5.04 12.5 mhz 2 2 4 0.08 5.28 6.25 mhz 3 3 8 0.16 5.76 3.125 mhz 4 5 32 0.64 8.64 781 khz 5 6 64 1.28 12.48 390 khz 6 7 128 2.56 20.16 195 khz 7 8 256 5.12 35.52 98 khz 1.2.5 vco output mute function the output mute function enables the HMC833LP6GE to disable the vco output while maintaining the pll and vco subsystems fully functional. the mute function provides over 40 db of isolation throughout the operating range of the HMC833LP6GE. to mute the output of the HMC833LP6GE, the following register writes are necessary: 1. initially, and only once, typically after power-up, pre-confgure the vco subsystem by writing vco_ reg 01h [8:0] = 3h (accomplished by writing to reg 05h = 188h). this write effectively enables the master enable, and pll buffer enable, and disables the manual mode rf buffer, divide-by 1, and rf divider of the vco subsystem, as shown in figure 27 . although this write disables the manual mode for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 21 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz enables of the vco subsystem, it has no affect on the pll or vco subsystem because typically and by default the vco subsystem is operating in auto mode. 2. then to mute the pll output simply write vco_reg 03h [ 2] = 1 (accomplish by writing to pll reg 05h = 2a18h in doubler mode, and reg 05h = 2a98h in fundamental mode of the vco), which effectively places the vco subsystem in manual mode. manual mode enables have been pre-confgured in step 1 to mute the pll output. 3. if it is required to tune the HMC833LP6GE while the output is muted a fnal write, reg 05h = 0h, is required. to enable the HMC833LP6GE output after muting: 1. write vco_reg 03h [ 2] = 0 (accomplish by writing to pll reg 05h = 2818h in doubler mode, or reg 05h = 2898h in fundamental mode). 2. a fnal write to reg 05h = 0h is required. please refer to figure 27 for more information. also note that the vco subsystem registers are not directly accessible. they are written to the vco subsystem via pll reg 05h . more information about vco subsystem spi in section 1.19 . 1.3 vco built in test with autocal the frequency limits of the vco can be measured using the bist features of the autocal machine. this is done by setting reg 0ah [10]=1 which freezes the vco switches in one position. vco switches may then be written manually, with the varactor biased at the nominal mid-rail voltage used for autocal. for example to measure the vco maximum frequency use switch 0, written to the vco subsystem via reg 05h =[000000000 0000 vcoid]. where vcoid = 000b. if autocal is enabled, ( reg 0ah [11] = 0), and a new frequency is written, autocal will run, but with switches frozen. the vco frequency error relative to the command frequency will be measured and results written to re g 11h [19:0] where re g 11h [19] is the sign bit. the result will be written in terms of vco count error (eq 4) . for example if the expected vco is 2 ghz, reference is 50 mhz, and n is 6, we expect to measure 2560 counts. if we measure a difference of -5 counts in re g 11h , then it means we actually measured 2555 counts. hence the actual frequency of the vco is 5/2560 low, or 1.99609375 ghz, 1 count ~ 781 khz. 1.4 spurious performance 1.4.1 integer operation and reference spurious the vco always operates at an integer multiple of the pd frequency in an integer synthesizer. in general, spurious signals originating from an integer synthesizer can only occur at multiples of the pd frequency. these unwanted outputs closest to the carrier are often simply referred to as reference sidebands. unwanted reference harmonics can also exist far from the carrier due to circuit isolation. spurs unrelated to the reference frequency must originate from outside sources. external spurious sources can modulate the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. it can also simply add to the output of the pll. reference spuri ous levels are typically below -100 dbc with a well designed board layout. a regulator with low noise and high power supply rejection, such as the hmc1060lp3e, is recommended to minimize external spurious sources. reference spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the synthesizer. typical board layout, regulator design, eval boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board, from those rec - ommended by hittite, can result in higher spurious levels. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 22 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz if the application environment contains other interfering frequencies unrelated to the pd fre quency, and if the application isolation from the board layout and regulation are insufficient, the unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurious emissions. the level of these emissions is dependant upon isolation and supply regulation or rejection (psrr). 1.4.2 fractional operation and spurious unlike an integer pll, spurious signals in a fractional pll can occur due to the fact that the vco operates at frequencies unrelated to the pd frequency. hence intermodulation of the vco and the pd harmonics can cause spurious sidebands. spurious emissions are largest when the vco operates very close to an integer multiple of the pd. when the vco operates exactly at a harmonic of the pd then, no in-close mixing products are present. as shown in figure 32 , interference is always present at multiples of the pd frequency, f pd , and the vco frequency, f vco . the difference, , between the vco frequency and the nearest har monic of the reference, will create what are referred to as integer boundary spurs. depending upon the mode of operation of the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (sub- harmonics) of the pd frequency. that is, fractional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and d4 spurs are small or unmeasurable. the worst case, in fractional mode, is when d=0, and the vco frequency is offset from nf pd by less than the loop bandwidth. this is the in-band integer boundary case. figure 36. fractional spurious example characterization of the levels and orders of these products is not unlike a mixer spur chart. exact levels of the products are dependent upon isolation of the various synthesizer parts. hittite can offer guidance about expected levels of spurious with HMC833LP6GE evaluation boards. regulators with high power supply rejection ratios (psrr) are recommended, especially in noisy applications. 1.4.2.1 charge pump and phase detector spurious considerations charge pump and phase detector linearity are of paramount importance when operating in fractional mode. any non-linearity degrades phase noise and spurious performance. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 23 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz we defne zero phase error when the reference signal and the divider vco signal arrive at the phase detector at the same time. phase detector linearity degrades when the phase error is very small and when the random phase errors cause the phase detector to switch back an forth between reference lead and vco lead. these switching non-linearities in fractional mode are eliminated by operating the phase detector with an average phase offset such that either the reference or vco always leads. a programmable charge pump offset current source is used to add dc current to the loop flter and create the desired phase offset. positive current causes the vco to lead, negative current causes the reference to lead. the offset charge pump is controlled via reg 09h . the phase offset is scaled from 0 degrees, that is the reference and the vco path arrive in phase, to 360 degrees, where they arrive a full cycle late. the offset can also be thought of in absolute time difference between the arrivals. the recommended operating point for the charge pump in fractional mode is one where the time offset at the phase detector is ~2.5ns + 4t vco , where t vco is the rf period at the fractional prescaler input. the required cp offset current should never exceed 25% of the programmed cp current. the specifc level of charge pump offset current reg 09h [20:14] is determined by this time offset, the comparison frequency and the charge pump current: ( ) ( ) ( ) 9 2.5 10 4 sec ,0.25 required cp offset min vco comparison cp cp t fi i ? ?? ? +? ? ? ? ?? ?? = where: t vco : is the rf period at the fractional prescaler input i cp : is the full scale current setting of the switching charge pump reg 09h [6:0] reg 09h [13:7] (eq 9) operation with charge pump offset infuences the required confguration of the lock detect function. refer to the description of lock detect function in section 1.11 . note that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences < 25 % in center frequencies. another factor in the spectral performance in fractional mode is the choice of the delta-sigma modulator mode. mode a can offer better in-band spectral performance (inside the loop bandwidth) while mode b offers better out of band performance. see reg 06h [3:2] for dsm mode selection. finally, all fractional synthesizers cre ate fractional spurs at some level. hittite offers the lowest level fractional spurious in the indus try in an integrated solution. 1.4.2.2 spurious related to channel step size (channel spurs) many fractional plls also create spurious emissions at offsets which are multiples of the channel step size. we refer to these as channel spurs. it is common in the industry to set the channel step size by use of the so-called modulus. for example, channel step size of 100 khz requires a small modulus related to the step size, and often results in 100 khz channel spurs. the HMC833LP6GE uses a large fxed modulus unrelated to the channel step size. as a result, the HMC833LP6GE has extremely low or unmeasurable channel spurs. in addition exact frequency mode ( 1.12.2.2 ) allows exact channel step size with no channel spurs. the lack of channel spurs means that the HMC833LP6GE has large regions of operation between integer boundaries with little or no spurs of any kind. large spurious free zones enable the HMC833LP6GE to be used with a tunable reference, to effectively move the spur free zones and hence achieve spur-free operation at all frequencies. the resulting pll is virtually spur-free at all frequencies. for more information see 1.4.2.3 . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 24 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.4.2.3 spurious reduction with tunable reference section 1.4.2 discussed fractional mode integer boundary spurious caused by vco operation near reference harmonics. it is possible, with hittite fractional synthesizers, to virtually eliminate the integer boundary spurious at a given vco frequency by changing the frequency of the reference. the reference frequency is normally generated by a crystal oscillator and is not tunable. however, hittite wideband plls with integrated vcos, including HMC833LP6GE, can be used as a high-quality tunable reference source, as shown in figure 33 . figure 37. tunable reference source with the setup shown in figure 33 , the HMC833LP6GE is capable of operating across all of its frequency range without sacrifcing phase noise, while virtually eliminating spurious emissions. optimum operation requires appropriate confguration of the two synthesizers to achieve this performance. hittite apps-support can assist with the required algorithms for ultra-low spurious tunable reference applications. an HMC833LP6GE tunable reference pll typically uses a high frequency crystal reference for best performance. phase noise from the mc830lp6ge tunable reference output at 100 khz offset varies typically from -145 dbc at 100 mhz output to -157 dbc at 25 mhz output. this performance of HMC833LP6GE as a tunable reference is equivalent to the phase noise of high performance crystal oscillators. figure 38. phase noise performance of the HMC833LP6GE -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) when used with a tunable reference source. (HMC833LP6GE operating at 3 ghz/30, 3 ghz/54, and 1.55 ghz/62 for the 100 mhz, 55.55 mhz, and 25 mhz curves respectively.) worst case spurious levels (largest spurs at any offset) of conventional fxed reference vs. a tunable reference can be compared by multiple individual phase noise measurements and summarized on a single plot vs. carrier frequency. for example, figure 35 shows the spectrum of a carrier operating at 2000.1 mhz with a 50 mhz fxed reference. this case is 100 khz away from an integer boundary (50 mhz x 40). worst case spurious can be observed at 100 khz offset and about -52 dbc in magnitude. figure 36 shows the same HMC833LP6GE pll vco operating at the same 2000.1 mhz carrier frequency, using a tunable reference at 47.5 mhz generated by hmc830lp6ge. worst case spurious in this case can be observed at 5 mhz offset and about -100 dbc in magnitude. the results of figure 35 and figure 36 show that the tunable reference source achieves 50 db better spurious performance, while maintaining essentially the same phase noise performance. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 25 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (a) 2000.1 mhz carrier frequency worst spur at 100 khz offset at ~-52 dbc with 50 mhz crystal -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (b) 2000.1 mhz carrier frequency worst spur at 5 khz offset at -100 dbc with tunable crystal figure 39. HMC833LP6GE worst spur at any offset, fxed 50 mhz reference, output frequency = 2000.1 mhz figure 40. HMC833LP6GE worst spur at any offset, tunable reference (hmc830lp6ge), output frequency = 2000.1 mhz many spurious measurements, such as the ones in figure 35 and figure 36 can be summarized into a single plot of worst case spurious at any offset vs. carrier frequency as shown in figure 37 . a log frequency display relative to the 2000 mhz fxed reference integer boundary was used to emphasize the importance of the loop bandwidth on spurious performance of the fxed reference case. this technique clearly shows the logarithmic roll-off of the worst case spurious when operating near the integer boundary. in this case the loop flter bandwidth of the HMC833LP6GE was 100 khz. figure 41. -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000k fixed 50 mhz reference tunable reference worst spur (dbc) output frequency (a) (b) largest observed spurious, at any offset, using a fxed 50 mhz reference source and a tunable reference source. for example worst case spurious operating at 2000.1 mhz (point (a)) in figure 35 with a fxed 50 mhz reference) is represented by a single point in figure 37 (point (a)) on the blue curve. similarly, worst case spurious from figure 36 with variable reference, operating at 2000.1 mhz is represented by a single point in figure 37 (point (b)) on the green curve. the plot in figure 37 is generated by tuning the carrier frequency away from integer boundary and recording the worst case spurious, at any offset, at each operating frequency. figure 37 shows that the worst case spurious for the 50 mhz fxed reference case, is nearly constant between -51 dbc and -55 dbc when operating with a carrier frequency less than 100 khz from the integer boundary (blue curve). it also shows that the worst case spurious rolls off at about 25 db/decade relative to 1 loop bandwidth. for example, at an operating frequency of 2001 mhz (equivalent to 10 loop bandwidths offset) worst case spurious is -80 dbc. similarly, at an operating frequency of 2010 mhz (equivalent to 100 loop bandwidths) worst case spurious is -100 dbc. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 26 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz in contrast, the green curve of figure 37 shows that the worst case spurious over the same operating frequency range, when using an hmc830lp6ge tunable reference, is below -100 dbc at all operating frequencies! in general all fractional plls have spurious when operating near integer boundaries. high performance tunable reference makes it possible to operate HMC833LP6GE, virtually spur-free at all frequencies, with little or no degradation in phase noise. 1.5 integrated phase noise & jitter the standard deviation of vco signal jitter may be estimated with a simple approximation if it is assumed that the locked vco has a constant phase noise, o | 2 ( f o ), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll-off at greater offsets. the simple locked vco phase noise approximation is shown on the left of figure 38 . figure 42. pll with integrated vco phase noise & jitter with this simplifcation the total integrated vco phase noise, o | 2 , in rads 2 in the linear form is given by o | 2 = o | 2 (f o ) b (eq 10) where o | 2 (f o ) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, and b is the 3 db corner frequency of the closed loop pll the integrated phase noise at the phase frequency detector, o | 2 pd is just scaled by n 2 /n 2 = o | 2 pd o | 2 (eq 11) the rms phase jitter of the vco in rads, o | , is just the square root of the phase noise integral. since the simple integral of (eq 10) is just a product of constants, we can easily do the integral in the log domain. for example if the vco phase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio is 100, then the integrated phase noise at the phase frequency detector, in db, is given by: o | 2 = 10log ( o | 2 ( f o )b/n 2 ) = -100 + 50 + 5 - 40 = -85 dbc pddb or equivalently, o | = 1 0 -85/20 = 53.6e-6 rads = 3.2e-3 degrees. while the phase noise reduces by a factor of 20logn after division to the reference, due to the increased period of the pd reference signal, the jitter is constant. the rms jitter from the phase noise is then given by t jpn = t pd o | pd /2 (eq 12) in this example if the pd reference was 50 mhz, t pd = 20ns, and hence t jpn = 179 femto-sec. it should be noted that this last expression is based upon a closed form integral of the entire spectrum of the oscillator phase noise. this integral starts at dc. it is common for real system to evaluate jitter over for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 27 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz shorter intervals of time, hence the integral often starts at some fnite frequency offset and will produce a jitter that is less than that given by the full expression. finally real oscillators have noise foors that also contribute to jitter. the phase noise of a white noise foor is a simple integral of noise foor density times bandwidth of interest to the system. this additional noise power should be added to the expression of (eq 16) to give a more accurate jitter number. depending upon the bandwidth of the system in question this noise foor contribution may be an important factor. 1.6 reference input stage figure 43. reference path input stage the reference buffer provides the path from an external reference source (generally crystal based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation controlled by reg 08h [21]. high gain ( reg 08h [21] = 0), recommended below 200 mhz, and high frequency ( reg 08h [21] = 1), for 200 to 350 mhz operation. the buffer is internally dc biased, with 100 internal termination. for 50 match, an external 100 resistor to ground should be added, followed by an ac coupling capacitor (impedance < 1 ), then to the xrefp pin of the part. at low frequencies, a relatively square reference is recommended to keep the input slew rate high. at higher frequencies, a square or sinusoid can be used. the following table shows the recommended operating regions for different reference frequencies. if operating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1, the pulse width should be (2.5ns + 8t ps ), where t ps is the period of the vco at the prescaler input. when r > 1 minimum pulse width is 2.5 ns. table 2. reference sensitivity table square input sinusoidal input reference input frequency (mhz) slew > 0.5v/ns recommended swing (vpp) recommended power range (dbm) recommended min max recommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1. 2 2.5 yes 3 8 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 28 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz input referred phase noise of the pll when operating at 50 mhz is between -150 and -156 dbc/hz at 10 khz offset depending upon the mode of operation. the input reference signal should be 10 db better than this foor to avoid deg radation of the pll noise contribution. it should be noted that such low levels are only necessary if the pll is the dominant noise contributor and these levels are required for the system goals. 1.7 reference path r divider the reference path r divider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled by rdiv ( reg 02h ). minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1, the pulse width should be (2.5 ns + 8tps), where tps is the period of the vco at the prescaler input. when r > 1 minimum pulse width is 2.5 ns. 1.8 rf path n divider the main rf path divider is capable of average divide ratios between 2 19 -5 (524,283) and 20 in fractional mode, and 2 19 -1 (524,287) to 16 in integer mode. the vco frequency range divided by the minimum n divider value will place practical restrictions on the maximum usable pd frequency. for example a vco operating at 1.5 ghz in fractional mode with a minimum n divider value of 20 will have a maximum pd frequency of 75 mhz. 1.9 charge pump & phase detector the phase detector (pd) has two inputs, one from the reference path divider and one from the rf path divider. when in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. we refer to the frequency of operation of the pd as f pd . most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the pd, f pd . f pd is also referred to as the comparison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians (360) of input phase difference. 1.10 phase detector functions phase detector register reg 0bh allows manual access to control special phase detector features. pd_up_en ( reg 0bh [5]), if 0, masks the pd up output, which prevents the charge pump from pumping up.` pd_dn_en ( reg 0bh [6]), if 0, masks the pd down output, which prevents the charge pump from pumping down. clearing both pd_up_en and pd_dn_en effectively tri-states the charge pump while leaving all other functions operating internally. pd force up reg 0bh [9] = 1 and pd force dn reg 0bh [10] = 1 allows the charge pump to be forced up or down respectively. this will force the vco to the ends to the tuning range which can be useful in test of the vco. 1.11 phase detector window based lock detect lock detect enable reg 07h [3]=1 is a global enable for all lock detect functions. the window based lock detect circuit effectively measures the difference between the arrival of the reference and the divided vco signals at the pd. the arrival time difference must consistently be less than the lock detect window length, to declare lock. either signal may arrive frst, only the difference in arrival times is counted. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 29 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.11.1 analog window lock detect the lock detect window may be generated by either an analog one shot circuit or a digital one shot based upon an internal timer. setting reg 07h [6]=0 will result in a fxed, analog, nominal 10 ns window, as shown in figure 40 . the analog window cannot be used if the pd rate is above 50 mhz, or if the offset is too large. figure 44. normal lock detect window - integer mode, zero offset for example a 25 mhz pd rate with a 1 ma charge pump setting ( reg 09h [6:0]= reg 09h [13:7]= 32h) and 400 a offset down current ( reg 09h [20:14]= 50h reg 09h [22]= 1) , would have an offset of about 400/1000 = 40% of the pd period or about 16 ns. in such an extreme case the divided vco would arrive 16 ns after the pd reference, and would always arrive outside of the 10 ns lock detect window. in such a case the lock detect circuit would always read unlocked, even though the vco might be locked. when using the 10 ns analog lock detect window, with a 40 ns pd period, the offset must always be less than 25% of the charge pump setting, 20% to allow for tolerances. hence a 1 ma charge pump setting can not use more than 200 a offset with a 25 mhz pd and an analog lock detect window. charge pump current, charge pump offset, phase detector rate and lock detect window are related. 1.11.2 digital window lock detect setting reg 07h [6]=1 will result in a variable length lock detect window based upon an internal digital timer. the timer period is set by the number of cycles of the internal ld clock as programmed by reg 07h [9:7]. the ld clock frequency is adjustable by reg 07h [11:10]. the ld clock signal can be viewed via the gpo test pins. refer 1.16 for details. 1.11.3 declaration of lock wincnt_max in reg 07h [2:0] defnes the number of consecutive counts of the divided vco that must land inside the lock detect window to declare lock. if for example we set wincnt_max = 2048, then the vco arrival would have to occur inside the window 2048 times in a row to be declared locked, which would result in a lock detect flag high. a single occurrence outside of the window will result in an out of lock, i.e. lock detect flag low. once low, the lock detect flag will stay low until the wincnt_max = 2048 condition is met again. the lock detect flag status is always readable in reg 12h [1] , if locked = 1. lock detect status is also output to the ld_sdo pin if reg 0fh [4:0]=1 . again, if locked, ld_sdo will be high. setting reg 0fh [6]=0 will display the lock detect flag on ld_sdo except when a serial port read is requested, in which case the pin reverts temporarily to the serial data out pin, and returns to the lock detect flag after the read is completed. refer to 1.11.5 for timing of the lock detect information. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 30 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.11.4 phase offset & fractional linearity when operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in integer mode. the phase detector linearity is degraded when operating with zero phase offset. hence in fractional mode it is necessary to offset the phase of the pd reference and the vco at the phase detector. in such a case, for example with an offset delay, as shown in figure 41 , the vco arrival will always occur after the reference. the lock detect circuit window may need to be adjusted to allow for the delay being used. for details see section digital lock detect with digital window example . figure 45. lock detect window - fractional mode with offset 1.11.5 digital lock detect with digital window example typical digital lock detect window widths are shown in table 3 . lock detect windows typically vary 10% vs voltage and 25% over temperature (-40c to +85c). table 3. typical digital lock detect window ld timer speed reg07[11:10] digital lock detect window nominal value 25% (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 1.7 9.2 13.3 22 38 72 138 272 slowest 11 7.6 10.2 15.4 26 47 88 172 338 ld timer divide setting reg07[9:7] 0 1 2 3 4 5 6 7 ld timer divide value 0.5 1 2 4 8 16 32 64 as an example, in fractional mode, with a 50 mhz pd, with a charge pump gain of 2 ma and a down leakage of -400 a ( reg 09h [13:7] = 64h, reg 09h [6:0] = 64h, reg 09h [20:14] = 50h, reg 09h [22] = 1), the average offset at the pd will be -0.400/2 = 0.2 of the pd period, or about 4 ns 25%. hence, when in lock, the divided vco will arrive at the pd about 4 ns after the divided reference. the lock detect window always starts on the arrival of the frst signal at the pd, in this case the reference. the lock detect window must be longer than 4 ns + 25% and shorter than the period of the pd, in this example, 20 ns. a perfect lock detect window would be the geometric mean or 9.8 ns. a comfortable solution of 12.8 ns with timer speed set at reg 07h [11:10]=1 and timer divider reg 07h [9:7]=2 works well for the example pd frequency and charge pump offset setting. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 31 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz tolerance on the window is +25% at +85 c, -25% at -40 c. here 12.8 ns nominal window may extend by +25% at +85c to 16 ns, which is fne for a pd period of 20 ns. also the minimum window may shrink by 25% to 9.6 ns at -40c, which again works well for the worst case offset of 4.6 ns. figure 46. lock detect window example with 50 mhz pd and 3.9 ns vco offset there is always a good solution for the lock detect window for a given operating point. the user should understand however that one solution does not ft all operating points. if charge pump offset or pd frequency are changed signifcantly then the lock detect window may need to be adjusted. 1.11.6 cycle slip prevention (csp) when changing vco frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two pd inputs are different, and the phase difference of the two inputs at the pd varies rapidly over a range much greater than 2 radians. since the gain of the pd varies linearly with phase up to 2, the gain of a conventional pd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. the output current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. the charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency actually reverse temporarily during locking. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle slipping increases the time to lock to a value greater than that predicted by normal small signal laplace analysis. the synthesizer pd features an ability to reduce cycle slipping during acquisition. the cycle slip preven - tion (csp) feature increases the pd gain during large phase errors. the specifc phase error that triggers the momentary increase in pd gain is set via reg 0bh [8:7] 1.11.7 charge pump gain a simplifed diagram of the charge pump is shown in figure 43 . charge pump up and down gains are set by cp dn gain and cp up gain respectively ( reg 09h [6:0] and reg 09h [13:7]) . the current gain of the pump in amps/radian is equal to the gain setting of this register divided by 2. for example if both cp dn gain and cp up gain are set to 50d the output current of each pump will be 1 ma and the phase frequency detector gain k p = 1 ma/2 radians, or 159 a/rad. see section 1.4 for more information. 1.11.8 charge pump phase offset - fractional mode in integer mode, the phase detector operates with zero offset. the divided reference signal and the divided vco signal arrive at the phase detector inputs at the same time. in fractional mode of operation, charge pump linearity and ultimately, phase noise, is much better if the vco and reference inputs are operated for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 32 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz with a phase offset. a phase offset is implemented by adding a constant dc offset current at the output of the charge pump. dc offset may be added to the up or dn switching pumps using reg 09h [21] or reg 09h [22] . the magnitude of the offset is controlled by reg 09h [20:14], and can range from 0 to 635 a in steps of 5 a. down offset is highly recommended in fractional mode of operation. integer mode of operation works best with zero offset. as an example, a pd comparison of f pd = 50 mhz (20 ns period) with the main pump gain set at 2 ma, and a down (dn) offset of -385 a would represent a phase offset of about (-385/2000)*360 = -69 degrees. this is equivalent to the divided vco arriving 3.8 ns after the reference at the pd input. it is critical that phase offset be used in fractional mode. normally, down offsets larger than 3 ns are typical. if the charge pump gain is changed, for example to compensate for changes in vco sensitivity, it is recommended to change the charge pump offset proportionally to maintain a constant phase offset. figure 47. charge pump gain & offset control 1.12 frequency tuning HMC833LP6GE vco subsystem always operates in fundamental frequency of operation (1500 mhz to 3000 mhz). the HMC833LP6GE generates frequencies below its fundamental frequency (25 mhz to 1500 mhz) by tuning to the appropriate fundamental frequency and selecting the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_reg 02h [5:0]. conversely the HMC833LP6GE generates frequencies greater than its fundamental frequency (3000 mhz to 6000 mhz) by tuning to the appropriate fundamental frequency and enabling the doubler mode ( vco_reg 03h [0] = 1 ). the HMC833LP6GE automatically controls frequency tuning in the fundamental band of operation, for more information see 1.2.1 vco auto-calibration (autocal) . to tune to frequencies below the fundamental frequency range (<1500 mhz) it is required to tune the HMC833LP6GE to the appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_reg 02h [5:0]. similarly, to tune to frequencies above the fundamental frequency range (> 3000 mhz) it is required to tune the HMC833LP6GE to the appropriate fundamental frequency, and then enable the doubler mode of operation ( vco_reg 03h [0] = 1 ). 1.12.1 integer mode the HMC833LP6GE is capable of operating in integer mode. for integer mode set the following registers a. disable the fractional modulator, reg 06h [11]= 0 b. bypass the modulator circuit, reg 06h [7]=1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 33 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz in integer mode the vco step size is fxed to that of the pd frequency, f pd . integer mode typically has 3 db lower phase noise than fractional mode for a given pd operating frequency. integer mode, however, often requires a lower pd frequency to meet step size requirements. the fractional mode advantage is that higher pd frequencies can be used, hence lower phase noise can often be realized in fractional mode. charge pump offset should be disabled in integer mode. 1.12.1.1 integer frequency tuning in integer mode the digital ? modulator is shut off and the n ( reg 03h ) divider may be programmed to any integer value in the range 16 to 2 19 -1. to run in integer mode confgure reg 06h as described, then program the integer portion of the frequency as explained by (eq 13) , ignoring the fractional part. a. disable the fractional modulator, reg 06h [11] = 0 b. bypass the delta-sigma modulator reg 06h [7] = 1 c. to tune to frequencies (<1500 mhz), select the appropriate output divider value vco_reg 02h [5:0]. d. to tune to frequencies (>3000 mhz), enable the doubler mode of operation ( vco_reg 03h [0] = 1). writing to vco subsystem registers ( vco_reg 02h [5:0] and vco_reg 03h [0] in this case ) is accomplished indirectly through pll register 5 ( reg 05h ). more information on communicating with the vco subsystem through pll reg 05h is available in 1.19 vco serial port interface (spi) section. 1.12.2 fractional mode the HMC833LP6GE is placed in fractional mode by setting the following registers: a. enable the fractional modulator, reg 06h [11]=1 b. connect the delta sigma modulator in circuit, reg 06h [7]=0 1.12.2.1 fractional frequency tuning this is a generic example, with the goal of explaining how to program the output frequency. actual variables are dependant upon the reference in use. the HMC833LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference. the frequency of the HMC833LP6GE, f vco , is given by f vco = ( n int + n frac ) = f int + f frac f xtal r (eq 13) f out = f vco / k (eq 14) where: f out is the output frequency after any potential dividers or doublers. k is 0.5 for doubler, 1 for fundamental, or k = 1,2,4,6,58,60,62 according to the vco subsystem type n int is the integer division ratio, reg 03h , an integer number between 20 and 524,284 n frac is the fractional part, from 0.0 to 0.99999...,n frac = reg 04h /2 24 r is the reference path division ratio, reg 02h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 34 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz f xtal is the frequency of the reference oscillator input f pd is the pd operating frequency, f xtal /r as an example: f out 1402.5 mhz k 2 f vco 2,805 mhz f xtal = 50 mhz r = 1 f pd = 50 mhz n int = 56 n frac = 0.1 reg 04h = round(0.1 x 2 24 ) = round(1677721.6) = 1677722 f vco = ( 56 + ) = 2805 mhz + 1.92 hz error 1677722 2 24 50e6 1 (eq 15) f out = = 1402.5 mhz + 0.596 hz error f vco 2 (eq 16) in this example the output frequency of 1402.5 mhz is achieved by programming the 19-bit binary value of 56d = 38h into intg_reg in reg 03h , and the 24-bit binary value of 1677722d = 19999ah into frac_reg in reg 04h . the 0.596 hz quantization error can be eliminated using the exact frequency mode if required. in this example the output fundamental is divided by 2. specifc control of the output divider is required. see section 3.0 and description for more details. 1.12.2.2 exact frequency tuning due to quantization effects, the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example, a 24 bit fractional modulator has frequency resolution set by the phase detector (pd ) comparison rate divided by 2 24 . the value 2 24 in the denominator is sometimes referred to as the modulus. hittite plls use a fxed modulus which is a binary number. in some types of fractional plls the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). for this reason hittite plls use a large fxed modulus. normally, the step size is set by the size of the fxed modulus. in the case of a 50 mhz pd rate, a modulus of 2 24 would result in a 2.98 hz step resolution, or 0.0596 ppm. in some applications it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tol erated. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary (eg. n = 50.0,50.5,50.25,50.75 etc.). unfortunately, some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. at f pd = 50 mhz this translates to 1.2 hz error. hittites exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to f pd /10 in reg 0ch to 10 (in this example). more generally, this feature can be used whenever the desired frequency, f vco , can be exactly represented on a step plan where there are an integer number of steps (<2 14 ) across integer-n boundaries. mathematically, this situation is satisfed if: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 35 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz gcd gcd gcd 1 14 mod 0 where gcd( , ) 2 pd pd vcok vco f f f f f f and f ?? ?? ?? ?? ?? ?? ?? = = (eq 17) where: gcd stands for greatest common divisor f n = maximum integer boundary frequency < f vco1 f pd = frequency of the phase detector and f vcok are the channel step frequencies where 0 < k < 2 24 -1, as shown in figure 44 . figure 48. exact frequency tuning some fractional plls are able to achieve this by adjusting (shortening) the length of the phase accumulator (the denominator or the modulus of the delta-sigma modulator) so that the delta-sigma modulator phase accumulator repeats at an exact period related to the interval frequency ( f vcok - f vco(k-1) ) in figure 44 . consequently, the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok - f vco(k-1) . for example, in some applications, these intervals might represent the spacing between radio channels, and the spurious would occur at multiples of the channel spacing. the hittite method on the other hand is able to generate exact frequencies between adjacent integer-n boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector comparison rate, which allows hittite plls to maintain excellent phase noise and spurious performance in the exact frequency mode. 1.12.2.3.3 using hittite exact frequency mode if the constraint in (eq 17) is satisfed, HMC833LP6GE is able to generate signals with zero frequency error at the desired vco frequency. exact frequency mode may be re-confgured for each target frequency, or be set-up for a fxed f gcd which applies to all channels. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 36 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.12.2.4.4 confguring exact frequency mode for a particular frequency 1. calculate and program the integer register setting reg 03h = n int = foor( f vco /f pd ), where the foor function is the rounding down to the nearest integer. then the integer boundary frequency f n = n int ? f pd 2. calculate and program the exact frequency register value reg 0ch = f pd /f gcd , where f gcd = gcd( f vco , f pd ) 3. calculate and program the fractional register setting reg 04h ( ) 24 2 ceil n vco frac pd ff n f ?? ?? ?? ?? ?? ? = = , where ceil is the ceiling function meaning round up to the nearest integer. example: to confgure the HMC833LP6GE for exact frequency mode at f vco = 2800.2 mhz where phase detector (pd) rate f pd = 61.44 mhz proceed as follows: check (eq 17) to confrm that the exact frequency mode for this f vco is possible. ( ) gcd gcd 14 6 66 3 gcd 14 gcd( , ) 2 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 pd pd vco f f f f and f f ?? ?? ?? ?? = = => = since (eq 17) is satisfed, the HMC833LP6GE can be confgured for exact frequency mode at f vco = 2800.2 mhz as follows: 1. n int = reg 03h = 6 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) 66 66 61.44 10 61.44 10 512 200 120000 gcd , gcd 2800.2 10 ,61.44 10 pd pd vco f dh ff = = = = 3. to program reg 04h , the closest integer-n boundary frequency f n that is less than the desired vco frequency f vco must be calculated. f n = f pd ? n int . using the current example: ( ) ( ) 6 24 6 6 24 6 45 61.44 10 2764.8 . 2 2800.2 10 2764.8 10 2 then reg04h 9666560 938000 61.44 10 int n pd n vco pd n f f mhz ff ceil ceil d h f ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = = = ? ? = = = = 1.12.2.5.5 hittite exact frequency channel mode if it is desirable to have multiple, equally spaced, exact frequency channels that fall within the same interval (ie. f n f vcok < f n+1 ) where f vcok is shown in figure 44 and 1 k 2 14 , it is possible to maintain the same integer-n ( reg 03h ) and exact frequency register ( reg 0ch ) settings and only update the fractional register ( reg 04h ) setting. the exact frequency channel mode is possible if (eq 17) is satisfed for at least two equally spaced adjacent frequency channels, i.e. the channel step size. to confgure the HMC833LP6GE for exact frequency channel mode, initially and only at the beginning, integer ( reg 03h ) and exact frequency ( reg 0ch ) registers need to be programmed for the smallest f vco frequency ( f vco1 in figure 44 ), as follows: 1. calculate and program the integer register setting reg 03h = n int = foor( f vco1 /f pd ), where f vco1 is shown in figure 44 and corresponds to minimum channel vco frequency. then the lower integer boundary frequency is given by f n = n int ? f pd . 2. calculate and program the exact frequency register value reg 0ch = f pd /f gcd, where f gcd = gcd(( f vcok+1 - f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing and the pd frequency (( f vcok+1 - f vcok ) and f pd ). then, to switch between various equally spaced intervals (channels) only the fractional register ( reg 04h ) needs to be programmed to the desired vco channel frequency f vcok in the following manner: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 37 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz reg 04h = ( ) 24 2 ceil n vcok frac pd ff n f ?? ?? ?? ?? ?? ? = where f n = foor( f vco1 /f pd ), and f vco1 , as shown in figure 44 , represents the smallest channel vco frequency that is greater than f n . example: to confgure the HMC833LP6GE for exact frequency mode for equally spaced intervals of 100 khz where frst channel (channel 1) = f vco1 = 2800.200 mhz and phase detector (pd) rate f pd = 61.44 mhz proceed as follows: first check that the exact frequency mode for this f vco1 = 2800.2 mhz (channel 1) and f vco2 = 2800.2 mhz + 100 khz = 2800.3 mhz (channel 2) is possible. ( ) ( ) gcd1 gcd1 gcd 2 gcd 2 12 14 14 6 66 3 gcd1 14 6 6 63 gcd 2 14 gcd( , ) gcd( , ) 22 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 61.44 10 gcd 2800.3 10 ,61.44 10 20 10 3750 2 pd pd pd pd vco vco ff f f f and f and f f f and f f f ?? ?? ?? ?? ?? ?? ?? ?? = = = => = = => = if (eq 17) is satisfed for at least two of the equally spaced interval (channel) frequencies f vco1 ,f vco2 ,f vco3 ,... f vcon , as it is above, hittite exact frequency channel mode is possible for all desired channel frequencies, and can be confgured as follows: 1. reg 03h = 6 1 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. reg 0ch = ( ) ( ) ( ) 66 36 1 61.44 10 61.44 10 3072 00 20000 gcd 100 10 ,61.44 10 gcd , pd pd vcok vcok f dc h f ff + = = = = ? where ( f vcok+1 - f vcok ) is the desired channel spacing (100 khz in this example). 3. to program reg 04h the closest integer-n boundary frequency f n that is less than the smallest channel vco frequency f vco1 must be calculated. f n = foor( f vco1 /f pd ). using the current example: 6 6 6 2800.2 10 45 61.44 10 2764.8 61.44 10 n pd f f floor mhz ?? ?? ?? ?? = = = then reg 04h ( ) ( ) 24 1 1 24 6 6 6 2 for channel 1 where 2800.2 2 2800.2 10 2764.8 10 9666560 938000 61.44 10 n vco vco pd ff ceil f mhz f ceil d h ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? = = ? = = = 4. to change from channel 1 ( f vco1 = 2800.2 mhz) to channel 2 ( f vco2 = 2800.3 mhz), only reg 04h needs to be programmed, as long as all of the desired exact frequencies f vcok ( figure 44 ) fall between the same integer-n boundaries ( f n < f vcok < f n+1 ). in that case reg 04h = ( ) 24 6 6 6 2 2800.3 10 2764.8 10 9693867 93 61.44 10 ceil d eaabh ?? ?? ?? ?? ?? ?? ? = = , and so on. 1.12.2.6 seed register & autoseed mode the start phase of the fractional modulator digital phase accumulator (dpa) may be set to one of four possible default values via the seed register reg 06h [1:0] . if autoseed reg 06h [8] is set, then the HMC833LP6GE will automatically reload the start phase into the dpa every time a new fractional frequency is selected. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 38 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz if autoseed is not set, then the HMC833LP6GE will start new fractional frequencies with the last value left in the dpa from the last frequency. hence the start phase will effectively be random. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed in the loop flter. for most cases a random, or non zero, non-binary start seed is recommended. further, since the autoseed always starts the accumulators at the same place, performance is repeatable if autoseed is used. reg 06h [1:0]=2 is recommended. 1.13 soft reset & power-on reset the HMC833LP6GE features a hardware power on reset (por). all chip registers will be reset to default states approximately 250 s after power up. the pll subsystem spi registers may also be soft reset by an spi write to register rst_swrst ( reg 00h ) . note that the soft reset does not clear the spi mode of operation referred to in section 1.17. 2 . it should be noted that the vco subsystem is not affected by the pll soft reset, the vco subsystem registers can only be reset by removing the power supply. note: if external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( reg 00h [5]=1) immediately after power up, before any other spi activity. this will ensure starting from a known state. 1.14 power down mode note that the vco subsystem is not affected by the cen or soft reset. hence device power down is a two step process. first power down the vco by writing 0 to vco register 1 via reg 05h and then power down the pll by pulling cen pin 17 low (assuming no spi overrides ( reg 01h [0]=1)). this will result in all analog functions and internal clocks disabled. current consumption will typically drop below 10 a in power down state. the serial port will still respond to normal communication in power down mode. it is possible to ignore the cen pin, by clearing rst_chipen_pin_select ( reg 01h [0]=0) . control of power down mode then comes from the serial port register rst_chipen_from_spi, reg 01h [1] . it is also possible to leave various blocks on when in power down (see reg 01h ) , including: a. internal bias reference sources reg 01h [2] b. pd block reg 01h [3] c. cp block reg 01h [4] d. reference path buffer reg 01h [5] e. vco path buffer reg 01h [6] f. digital i/o test pads reg 01h [7] to turn off the vco rf buffer but leave the vco running and the pll locked write reg 05h = 2a98(manual select) then write reg 05h = 0d88(disable vco rf buffer) to re-enable the rf buffer write reg 05h =0f88(enable vco rf buffer) 1.15 chip identifcation pll subsystem version information may be read by reading the content of read only register, chip_id in reg 00h . it is not possible to read the vco subsystem version. 1.16 general purpose output (gpo) pin the pll shares the ld_sdo (lock-detect/serial data out) pin to perform various functions. while the pin is most commonly used to read back registers from chip via the spi, it is also capable of exporting a variety of interesting signals and real time test waveforms (including lock detect). it is driven by a tri-state cmos driver with ~200 rout. it has logic associated with it to dynamically select whether the driver is enabled, for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 39 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz and to decide which data to export from the chip. in its default confguration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed spi reads. this allows it to share the output with other devices on the same bus. depending on the spi mode, the read section of spi cycle is recognized differently hmc spi mode: the driver is enabled during the last 24 bits of spi read cycle (not during write cycles). open spi mode: the driver is enabled if the chip is addressed - ie. the last 3 bits of spi cycle = 000b before the rising edge of sen (note a). to monitor any of the gpo signals, including lock detect, set reg 0fh [7] = 1 to keep the sdo driver always on. this stops the ldo driver from tri-stating and means that the sdo line cannot be shared with other devices. the chip will naturally switch away from the gpo data and export the sdo during an spi read (note b). to prevent this automatic data selection, and always select the gpo signal, set prevent automux of sdo ( reg 0fh [6] = 1). the phase noise performance at this output is poor and uncharacterized. also, the gpo output should not be toggling during normal operation. otherwise the spectral performance may degrade. note that there are additional controls available, which may be helpful if sharing the bus with other devices: ? to allow the driver to be active (subject to the conditions above) even when the chip is disabled - set reg 01h [7] = 0. ? to disable the driver completely, set reg 08h [5] = 0 (it takes precedence over all else). ? to disable either the pull-up or pull-down sections of the driver, reg 0fh [8] = 1 or reg 0fh [9] = 1 respectively. note a: if sen rises before sck has clocked in an invalid (non-zero) chip -address, the HMC833LP6GE will start to drive the bus. note b: in open mode, the active portion of the read is defned between the 1 st sck rising edge after sen, to the next rising edge of sen. example scenarios: ? drive sdo during reads, tri-state otherwise (to allow bus-sharing) ? no action required. ? drive sdo during reads, lock detect otherwise ? set gpo select reg 0fh [4:0] = 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1) ? always drive lock detect ? set prevent automux of sdo reg 0fh [6] = 1 ? set gpo select reg 0fh [4:0]= 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1)) the signals available on the gpo are selected by changing gpo select, reg 0fh [4:0]. 1.17 serial port 1.17.1 serial port modes of operation the HMC833LP6GE serial port interface can operate in two different modes of operation. a. hmcspi hmc mode (hmc legacy mode) - single slave per hmcspi bus b. hmcspi open mode - up to 8 slaves per hmcspi bus. both modes support 5-bits of register address space. hmc mode can support up to 6 bits of register for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 40 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz address. register 0 has a dedicated function in each mode. open mode allows wider compatibility with other manufacturers spi protocols. table 4. register 0 comparison - single vs multi-user modes single user hmc mode multi-user open mode read chip id 24-bits chip id 24-bits write soft reset, general strobes read address [4:0] soft reset [5] general strobes [23:6] 1.17. 2 hmcspi protocol decision after power-on reset on power up both types of modes are active and listening. a decision to select the desired spi protocol is made on the frst occurrence of sen or sclk following a hard reset, after which the protocol is fxed and only changeable by cycling the power off and on. a. if a rising edge on sen is detected frst hmc mode is selected. b. if a rising edge on sclk is detected frst open mode is selected. 1.17.3 serial port hmc mode - single pll hmc mode (legacy mode) serial port operation can only address and talk to a single pll, and is compatible with most hittite plls and plls with integrated vcos. the hmc mode protocol, shown in fgures figure 45 and figure 46 , is designed for a 4 wire interface with a fxed protocol featuring a. 1 read/write bit b. 6 address bits c. 24 data bits d. 3 wire for write only, 4 wire for read/write capability 1.17.3.1 hmc mode - serial port write operation avdd = dvdd = 3v 10%, agnd = dgnd = 0v table 5. spi hmc mode - write timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 sck to sen fall 10 ns max serial port clock speed 50 mhz a typical hmc mode write cycle is shown in figure 45 . a. the master (host) both asserts sen (serial port enable) and clears sdi to indicate a write cycle, followed by a rising edge of sck. b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen. sdi low indi cates a write cycle (/wr). c. host places the six address bits on the next six falling edges of sck, msb frst. d. slave shifts the address bits in the next six rising edges of sck (2-7). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 41 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz e. host places the 24 data bits on the next 24 falling edges of sck, msb frst. f. slave shifts the data bits on the next 24 rising edges of sck (8-31). g. the data is registered into the chip on the 32nd rising edge of sck. h. sen is cleared after a minimum delay of t 5 . this completes the write cycle. figure 49. hmc mode - serial port timing diagram - write 1.17.3 . 2 hmc mode - serial port read operation a typical hmc mode read cycle is shown in figure 46 . a. the master (host) asserts both sen (serial port enable) and sdi to indicate a read cycle, followed by a rising edge sclk. note: the lock detect (ld) function is usually multiplexed onto the ld_sdo pin. it is suggested that ld only be considered valid when sen is low. in fact ld will not toggle until the frst active data bit toggles on ld_sdo, and will be restored immediately after the trailing edge of the lsb of serial data out as shown in figure 46 . b. the slave (HMC833LP6GE) reads sdi on the 1st rising edge of sclk after sen. sdi high initiates the read cycle (rd) c. host places the six address bits on the next six falling edges of sclk, msb frst. d. slave registers the address bits on the next six rising edges of sclk (2-7). e. slave switches from lock detect and places the requested 24 data bits on sd_ldo on the next 24 rising edges of sck (8-31), msb frst . f. host registers the data bits on the next 24 falling edges of sck (8-31). g. slave restores lock detect on the 32nd rising edge of sck. h. de-assertion of sen completes the cycle table 6. spi hmc mode - read timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 sclk to sdo delay 8.2ns+0.2 ns/pf ns t 6 recovery time 10 ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 42 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz figure 50. hmc mode - serial port timing diagram - read 1.17.4 serial port open mode the serial port open mode, shown in figure 47 and figure 48 , features: a. compatibility with general serial port protocols that use shift and strobe approach to communication b. compatible with hittite pll with integrated vco solutions, useful to address multiple chips of various types from a single serial port bus. the open mode protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. wide compatibility with multiple protocols from multiple vendors c. simultaneous write/read during the spi cycle d. 5-bit address space e. 3 wire for write only capability, 4 wire for read/write capability hittite plls with integrated vcos support open mode. some legacy pll and microwave plls with integrated vcos only support hmc mode. consult the relevant data sheets for details. typical serial port operation can be run with sclk at speeds up to 50 mhz. 1.17.4.1 open mode - serial port write operation avdd = dvdd = 3v 10%, agnd = dgnd = 0v table 7. spi open mode - write timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk 32 rising edge to sen rising edge 10 ns t 6 recovery time 20 ns max serial port clock speed 50 mhz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 43 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz a typical write cycle is shown in figure 47 . a. the master (host) places 24-bit data, d23:d0, msb frst, on sdi on the frst 24 falling edges of sclk. b. the slave (HMC833LP6GE) shifts in data on sdi on the frst 24 rising edges of sclk c. master places 5-bit register address to be written to, r4:r0, msb frst, on the next 5 falling edges of sclk (25-29) d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master places 3-bit chip address, a2:a0, msb frst, on the next 3 falling edges of sclk (30-32). hittite reserves chip address a2:a0 = 000 for all rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32). g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. figure 51. open mode - serial port timing diagram - write 1.17.4 . 2 open mode - serial port read operation a typical read cycle is shown in figure 48 . in general, in open mode the ld_sdo line is always active during the write cycle. during any open mode spi cycle ld_sdo will contain the data from the current address written in reg0h[7:3]. if reg0h[7:3] is not changed then the same data will always be present on ld_sdo when an open mode cycle is in progress. if it is desired to read from a specifc address, it is necessary in the frst spi cycle to write the desired address to reg0h[7:3], then in the next spi cycle the desired data will be available on ld_sdo. an example of the open mode two cycle procedure to read from any random address is as follows: a. the master (host), on the frst 24 falling edges of sclk places 24-bit data, d23:d0, msb frst, on sdi as shown in figure 48 . d23:d5 should be set to zero. d4:d0 = address of the register to be read on the next cycle. b. the slave (HMC833LP6GE) shifts in data on sdi on the frst 24 rising edges of sclk c. master places 5-bit register address , r4:r0, (the read address register), msb frst, on the next 5 falling edges of sclk (25-29). r4:r0=00000. d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master places 3-bit chip address, a2:a0, msb frst, on the next 3 falling edges of sclk (30-32)..chip address is always 000 for rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 44 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. i. master clears sen to complete the the address transfer of the two part read cycle. j. if one does not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on sdi to register zero on the read back part of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling edges of sclk. l. slave (HMC833LP6GE) shifts the sdi data on the next 32 rising edges of sclk. m. slave places the desired read data (ie. data from the address specifed in reg 00h [7:3] of the frst cycle) on ld_sdo which automatically switches to sdo mode from ld mode, disabling the ld output. m. master asserts sen after the 32nd rising edge of sck to complete the cycle and revert back to lock detect on ld_sdo. table 8. spi open mode - read timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk rising edge to sdo time 8.2ns+0.2ns/pf ns t 6 recovery time 10 ns t 7 sck 32 rising edge to sen rising edge 10 ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 45 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 1.17.4 .3 hmcspi open mode read operation - 2 cycles figure 52. serial port timing diagram - read for more information on using the gpo pin while in spi open mode please see section 1.16. 1.18 confguration at start-up to confgure the pll after power up, follow the instructions below: 1. confgure the reference divider (write to reg 02h ), if required. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 46 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2. confgure the delta-sigma modulator (write to reg 06h ). ? confguration involves selecting the mode of the delta-sigma modulator (mode a or mode b), selection of the delta-sigma modulator seed value, and confguration of the delta-sigma modulator clock scheme. it is recommended to use the values found in the hittite pll evaluation board control software register fles. 3. confgure the charge pump current and charge pump offset current (write to reg 09h ) 4. confgure the vco subsystem (write to reg 05h , for more information see section 1.19 , and 3.0 vco subsystem register map . detailed writes to the vco subsystem via pll reg 05h at start-up are available in the register setting files found in the hittite pll evaluation software received with a product evaluation kit or downloaded from www.hittite.com . 5. program the frequency of operation ? program the integer part (write to reg 03h ) ? program the fractional part (write to reg 04h ) 6. confgure the vco output divider/doubler, if needed in the vco subsystem via pll reg 05h . once the HMC833LP6GE is confgured after startup, in most cases the user only needs to change frequencies by writing to reg 03h integer register, reg 04h fractional register, and reg 05h to change the vco output divider or doubler setting if needed, and possibly adjust the charge pump settings by writing to reg 09h . for detailed and most up-to-date start-up confguration please refer to the appropriate register setting files found in the hittite pll evaluation software received with a product evaluation kit or downloaded from www.hittite.com . 1.19 vco serial port interface (spi) the HMC833LP6GE communicates with the internal vco subsystem via an internal 16 bit vco serial port, (e.g. see figure 29 ). the internal serial port is used to control the step tuned vco and other vco subsystem functions, such as rf output divider / doubler control and rf buffer enable. note that the internal vco subsystem spi (vspi) runs at the rate of the autocal fsm clock, t fsm , (section 1. 2.1 ) where the fsm clock frequency cannot be greater than 50 mhz. the vspi clock rate is set by reg 0ah [14:13]. writes to the vcos control registers are handled indirectly, via writes to reg 05h of the pll. a write to pll reg 05h causes the pll subsystem to forward the packet, msb frst, across its internal serial link to the vco subsystem, where it is interpreted. the vco serial port has the capability to communicate with multiple subsystems inside the ic. for this reason each subsystem has a subsystem id, reg 05h [2:0]. each subsystem has multiple registers to control the functions internal to the subsystem, which may be different from one subsystem to the next. hence each subsystem has internal register addresses bits ( reg 05h [6:3]) finally the data required to confgure each register within the vco subsystem is contained in reg 05h [15:7]. 1.19.1 vspi use of reg05h the packet data written into, reg 05h is sub-parsed by logic at the vco subsystem into the following 3 felds: 1. [2:0] - 3 bits - vco_id, target subsystem address = 000b. 2. [6:3] - 4 bits - vco_regaddr, the internal register address inside the vco subsystem. 3. [15:7] - 9- bits- vco_data, data feld to write into the vco register. for example, to write 0_1111_1110 into register 2 of the vco subsystem (vco_id = 000b), and set the for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 47 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz vco output divider to divide by 62, the following needs to be written to reg 05h =0 _1111_1110, 0 010, 0 0 0 b. during autocal, the autocal controller only updates the data feld of reg 05h . the vco subsystem register address ( reg 05h [6:3]) must be set to 0000 for the autocal data to be sent to the correct address. vco subsystem id and register address are not modifed by the autocal state machine. hence, if a manual access is done to a vco subsystem register the user must reset the register address to zero before a change of frequency which will re-run autocal. since every write to reg 05h will result in a transfer of data to the vco subsystem, if the vco subsystem needs to be reset manually, it is important to make sure that the vco switch settings are not changed. hence the switch settings in reg 10h [7:0] need to be read frst, and then rewritten to reg 05h [15:8]. in summary, frst read reg 10h , then write to reg 05h as follows: reg 10h[7:0] = vv x yyyyy reg 05h = vv x yyyyy 0 0000 iii reg 05h [2:0] = iii, subsystem id, 3 bits (000) reg 05h [6:3] = 0000, subsystem register address reg 05h [7] = 0 , calibration tune voltage off reg 05h [12:8] = yyyyy, vco caps reg 05h [13] = x, dont care reg 05h [15:14] = vv, vco select for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 48 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.0 pll register map 2.1 reg 00h id register (read only) bit type name width default description [23:0] ro chip_id 24 a7975 HMC833LP6GE chip id 2.2 reg 00h open mode read address/rst strobe register (write only) bit type name width default description [4:0] wo read address 5 - (write only) read address for next cycle - open mode only [5] wo soft reset 1 - soft reset - both spi modes reset (set to 0 for proper operation) [23:6] wo not defned 18 - not defned (set to 0 for proper operation) 2.3 reg 01h rst register (default 000002h) bit type name width default description [0] r/w rst_chipen_pin_select 1 0 1 = take pll enable via cen pin, see power down mode description 0 = take pll enable via spi (rst_chipen_from_spi) reg01[1] [1] r/w rst_chipen_from_spi 1 1 spis pll enable bit [2] r/w keep_bias_on 1 0 when pll is disabled, keeps internal bias generators on, ignores chip enable control. [3] r/w keep_pd_on 1 0 when pll is disabled, keeps pd circuit on, ignores chip enable control [4] r/w ke e p_ cp_ o n 1 0 when pll is disabled, keeps charge pump on, ignores chip enable control [5] r/w keep_ref_buf_on 1 0 when pll is disabled, keeps reference buffer block on, ignores chip enable control [6] r/w keep_vco_on 1 0 when pll is disabled, keeps vco divider buffer on, ignores chip enable control [7] r/w keep_gpo_driver_on 1 0 when pll is disabled, keeps gpo output driver on, ignores chip enable control [8] r/w reserved 1 0 reserved [9] r/w reserved 1 0 reserved 2.4 reg 02h refdiv register (default 000001h) bit type name width default description [13:0] r/w rdiv 14 1 reference divider r value (eq 13)) divider use also requires refbufen reg08[3]=1and divider min 1d max 16383d for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 49 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.5 reg 03h frequency register - integer part (default 000019h) bit type name width default description [18:0] r/w intg 19 25d vco divider integer part, used in all modes, see (eq 13) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d integer mode min 16d max 2 19 -1 = 7ffffh = 524,287d 2.6 reg 04h frequency register - fractional part (default 000000h) bit type name width default description [23:0] r/w frac 24 0 vco divider fractional part (24-bit unsigned) see fractional frequency tuning used in fractional mode only (n frac = reg 04h /2 24 min 0d max 2 24 -1 2.7 reg 05h vco spi register (default 000000h) bit type name width default description [2:0] r/w vco subsystem_id, 3 0 internal vco subsystem id [6:3] r/w vco subsystem register address 4 0 for interfacing with the vco please see section 1.19 . [15:7] r/w vco subsystem data 9 0 note: reg05h is a special register used for indirect addressing of the vco subsystem. writes to reg05h are automatically forwarded to the vco subsystem by the vco spi state machine controller. reg05h is a read-write register. however, reg05h only holds the contents of the last transfer to the vco subsystem. hence it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. please take note special considerations for autocal related to reg05h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 50 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.8 reg 06h sd cfg register (default 200b4ah) bit type name width default description [1:0] r/w seed 2 2 selects the seed in fractional mode 00: 0 seed 01: lsb seed 02: b29d08h seed 03: 50f1cdh seed note; writes to this register are stored in the HMC833LP6GE and are only loaded into the modulator when a frequency change is executed and if autoseed reg06h[8] =1 [3:2] r/w order 2 2 select the modulator type 0: 1st order 1: 2nd order 2: type 1 mode b 3: type 2 mode a [6:4] r/w reserved 3 4 program to 7d [7] r/w frac_bypass 1 0 0: use modulator, required for fractional mode, 1: bypass modulator, required for integer mode note: in bypass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [8] r/w autoseed 1 1 1: loads the seed whenever the frac register is written 0: when frac register write changes frequency, modulator starts with previous contents [9] r/w clkrq_refdiv_sel 1 1 selects the modulator clock source- for test only 1: vco divider clock (recommended for normal operation) 0: ref divider clock ignored if bits [10] or [21] are set [10] r/w sd modulator clk select 1 0 0 - sd auxclk, 1- sd vco clock delay (recommended) [11] r/w sd enable 1 1 0: disable frac core, use for integer mode or integer mode with csp 1: enable frac core, required for fractional mode, or integer isolation testing this register controls whether autocal starts on an integer or a fractional write [12] r/w reserved 1 0 [13] r/w reserved 1 0 [15:14] r/w reserved 2 0 [17:16] r/w reserved 2 0 program to 3d [18] r/w bist enable 1 0 enable built in self test [20:19] r/w rdiv bist cycles 2 0 rdiv bist cycles 00: 1032 01: 2047 10: 3071 11: 4095 [21] r/w auto_clock_confg 1 1 set to 0 for f pd > 50 mhz [22] r/w reserved 1 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 51 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.9 reg 07h lock detect register (default 00014dh) bit type name width default description [2:0] r/w lkd_wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/w enable internal lock detect 1 1 see section 1.16 [5:4] r/w reserved 2 0 reserved [6] r/w lock detect window type 1 1 lock detection window timer selection 1: digital programmable timer 0: analog one shot, nominal 10 ns window [9:7] r/w ld digital window duration 3 2 0 lock detection - digital window duration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/w ld digital timer freq control 2 0 lock detect digital timer frequency control 00 fastest 11 slowest [12] r/w ld timer test mode 1 0 1: force timer clock on continuously - for test only 0: normal timer operation - one shot [13] r/w auto relock - one try 1 0 1: attempts to relock if lock detect fails for any reason only tries once. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 52 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.10 reg 08h analog en register (default c1beffh) bit type name width default description [0] r/w bias_en 1 1 enables main chip bias reference [1] r/w cp_en 1 1 charge pump enable [2] r/w pd_en 1 1 pd enable [3] r/w refbuf_en 1 reference path buffer enable [4] r/w vcobuf_en 1 1 vco path rf buffer enable [5] r/w gpo_pad_en 1 1 0 - pin ld_sdo disabled 1 - and regfh[7]=1 , pin ld_sdo is always on required for use of gpo port 1 - and regfh[7]=0 spi ldo_spi is off if unmatched chip address is seen on the spi, allowing a shared spi with other compatible parts [6] r/w reserved 1 1 reserved [7] r/w vco_div_clk_to_dig_en 1 1 vco divider clock to digital enable [8] r/w reserved 1 0 reserved [9] r/w prescaler clock enable 1 1 prescaler clock enable [10] r/w vco buffer and prescaler bias enable 1 1 vco buffer and prescaler bias enable [11] r/w charge pump internal opamp enable 1 1 should be programmed to 1 [14:12] r/w reserved 3 011 reserved [17:15] r/w reserved 3 011 reserved [18] r/w spare 1 0 spare [19] r/w reserved 1 0 reserved [20] r/w reserved 1 0 reserved program to 0 [21] r/w high frequency reference 1 0 program to 1 for xtal > 200 mhz [22] r/w reserved 1 1 reserved program to 1 [23] r/w reserved 1 1 reserved program to 1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 53 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2 .11 reg 09h charge pump register (default 403264h) bit type name width default description [6:0] r/w cp dn gain 7 100d 64h charge pump dn gain control 20 astep affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [13:7] r/w cp up gain 7 100d 64h charge pump up gain control 20 a per step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [20:14] r/w offset magnitude 7 0 charge pump offset control 5 a/step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 10 a ... 127d = 635 a [21] r/w offset up enable 1 0 recommended setting = 0 [22] r/w offset dn enable 1 1 recommended setting = 1 in fractional mode, 0 otherwise [23] r/w hikcp 1 0 hikcp high current charge pump for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 54 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.12 reg 0ah vco autocal confguration register (default 002205h) bit type name width default description [2:0] r/w vtune resolution 3 5 r divider cycles 0 - 1 1 - 2 2 - 4 ... 7 - 256 [5:3] r/w vco curve adjustment 3 0 vco curve adjustment vs temp for autocal 0 - disabled 1 : + 1 curve 2: +2 curves 3: +3 curves 4: -4 curves 5: -3 curves 6: -2 curves 7: -1 curve [7:6] r/w wait state set up 2 0 wait state setup 100 t fsm see section 1.2.4 t mmt = 1 measurement cycle of autocal 0: wait only at startup 1: wait on startup and after frst t mmt cycle 2: wait on startup and after frst two t mmt cycles 3: wait on startup and after frst three t mmt cycles [9:8] r/w num of sar bits in vco 2 0 number of sar bits in vco 0: 8 - recommended 1: 7 2: 6 3: 5 [10] r/w force curve 1 0 force curve sent during tuning tune from reg5 [11] r/w bypass vco tuning 1 0 bypass vco tuning [12] r/w no vspi trigger 1 0 dont trigger a transfer on writes to reg 05h [14:13] r/w fsm/vspi clock select 2 1 set the autocal fsm and vspi clock (50 mhz maximum) 0: input crystal reference 1: input crystal reference/4 2: input crystal reference/16 3: input crystal reference/32 [15] r/w xtal falling edge for fsm 1 0 use the falling edge of the xtal for fsm autocal clock - required for bist [16] r/w force rdivider bypass 1 0 force the r divider bypass for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 55 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.13 reg 0bh pd register (default 7c061h) bit type name width default description [2:0] r/w pd_del_sel 3 1 sets pd reset path delay (recommended setting 001) [3] r/w short pd inputs 1 0 shorts the inputs ot the phase frequency detector - test only [4] r/w pd_phase_sel 1 0 inverts the pd polarity (program to 0) 0- use with a positive tuning slope vco and passive loop filter (default) 1- use with a negative slope vco or with an inverting active loop filter with a positive slope vco [5] r/w pd_up_en 1 1 enables the pd up output [6] r/w pd_dn_en 1 1 enables the pd dn output [8:7] r/w csp mode 2 0 cycle slip prevention mode extra current is driven into the loop flter when the phase error is larger than: 0: disabled 1: 5.4ns 2: 14.4ns 3: 24.1ns this delay varies by +- 10% with temperature, and +- 12% with process. [9] r/w force cp up 1 0 forces cp up output on - use for test only [10] r/w force cp dn 1 0 forces cp dn output on - use for test only [11] r/w force cp mid rail 1 0 force cp mid rail - use for test only [14:12] r/w reserved 3 4 program to 100 [16:15] r/w cp internal opamp bias 2 3 program to 11 [18:17] r/w mcounter clock gating 2 3 mcounter clock gating 0: mcounter off 1: n<128 2: n< 1023 3: all clocks on (recommended setting 11) [19] r/w reserved 1 0 program to 0 [21:20] r/w reserved 2 0 program to 00 [23:22] r/w reserved 2 0 program to 00 2.14 reg 0ch exact frequency mode register (default 000000h) bit type name width default description [13:0] r/w number of channels per fpd 14 0 comparison frequency divided by the correction rate, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: disabled 1: disabled 2:16383d (3fffh) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 56 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.15 reg 0fh gpo_spi_rdiv register (default 000001h) bit type name width default description [4:0] r/w gpo_select 5 1d signal selected here is output to sdo pin when enabled 0: data from reg0f[5] 1: lock detect output 2. lock detect trigger 3: lock detect window output 4: ring osc test 5. pullup hard from csp 6. pulldn hard from csp 7. reserved 8: reference buffer output 9: ref divider output 10: vco divider output 11. modulator clock from vco divider 12. auxiliary clock 13. aux spi clock 14. aux spi enable 15. aux spi data out 16. pd dn 17. pd up 18. sd3 clock delay 19. sd3 core clock 20. autostrobe integer write 21. autostrobe frac write 22. autostrobe aux spi 23. spi latch enable 24. vco divider sync reset 25. seed load strobe 26.-29 not used 30. spi output buffer en 31. soft rstb [5] r/w gpo test data 1 0 1 - gpo test data [6] r/w prevent automux sdo 1 0 1- outputs gpo data only 0 - automuxes between sdo and gpo data [7] r/w ldo driver always on 1 0 1- ld_sdo pin driver always on 0 - ld_sdo pin driver only on during spi read cycle [8] r/w disable pfet 1 0 program to 0 [9] r/w disable nfet 1 0 program to 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 57 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 2.16 reg 10h vco tune register (default 000020h) bit type name width default description [7:0] ro vco switch setting 8 32 read only register. indicates the vco switch setting selected by the autocal state machine to yield the nearest free running vco frequency to the desired operating frequency. not valid when reg10h[8] = 1, autocal busy. note if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 256 = lowest frequency note: vco subsystems may not use all the msbs, in which case the unused bits are dont care [8] ro autocal busy 1 0 busy when autocal state machine is searching for the nearest switch setting to the requested frequency. 2.17 reg 11h sar register (default 007fffh) bit type name width default description [18:0] ro sar error mag counts 19 2 19 -1 sar error magnitude counts [19] ro sar error sign 1 0 sar error sign 0=+ve 1=-ve 2.18 reg 12h gpo2 register (default 000000h) bit type name width default description [0] ro gpo 1 0 gpo state [1] ro lock detect 1 0 lock detect status 1 = locked 0 = unlocked 2.19 reg 13h bist register (default 000000h) bit type name width default description [15:0] ro bist signature 19 4697d bist signature [16] ro bist busy 1 0 bist busy for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 58 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 3.0 vco subsystem register map please note that the vco subsystem uses indirect addressing via reg 05h . for more detailed information on how to write to the vco subsystem please see section 1.19 vco serial port interface (spi) . 3.1 vco_reg 00h tuning bit type name width default description [0] wo cal 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage [8:1] wo caps 8 16 vco sub-band selection. 0 - max frequency 1111 1111 - min fre quen cy. not all sub-bands are used on the various products. 3.2 vco_reg 01h enables bit type name width default description [0] wo master enable vco subsystem 1 1 0 - all vco subsystem blocks off manual mode ( vco_reg 03h [2] = 1) 1- anded with local enables only auto mode ( vco_reg 03h [2] = 0) 1- master enable ignores local enables [1] wo manual mode pll buffer enable 1 1 enables pll buffer in manual mode only [2] wo manual mode rf buffer enable 1 1 enables rf buffer to output in manual mode only [3] wo manual mode divide by 1 enable 1 1 enables rf divide by 1 in manual mode only [4] wo manual mode rf divider enable 1 1 enables rf divider in manual mode only [8:5] wo dont care 4 0 dont care for example, to turn disable the rf buffer in the vco subsystem and mute the output of the HMC833LP6GE, bit 2 in vco_reg01h needs to be cleared. if the other bits are left unchanged, then 0 0001 1011 needs to be written into vco reg01h. the vco subsystem register is accessed via a write to pll subsystem reg 05h = 0 0001 1011 0001 000 = d88h reg 05h [2:0] = 000; vco subsystem id 0 reg 05h [6:3] = 0001; vco subsystem register address reg 05h [7] = 1; master enable reg 05h [8] = 1; pll buffer enable reg 05h [9] = 0; disable rf buffer reg 05h [10] = 1; divide by 1 enable reg 05h [11] = 1; rf divider enable reg 05h [16:12] = 0; dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 59 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 3.3 vco_reg 02h biases bit type name width default description [5:0] wo rf divide ratio 6 1 0 - mute, vco and pll buffer on, rf output stages off 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 note: this register automatically controls the enables to the, rf output buffer, rf divider, rf divide by 1 path, and requires master enable ( vco_reg 01h [0] = 1) and autorfo mode ( vco_reg 03h [2] = 0) note: bit[0] is a dont care in manualrfo mode. [7:6] wo rf output buffer gain control 2 3 11 - max gain 10 - max gain - 3 db 01 - max gain - 6 db 00 - max gain - 9 db [8] wo divider output stage gain control 1 0 1 - max gain 0 - max gain - 3 db used to fatten the output power level across frequency ? for divide-by 1 or divide-by 2 it is recommended to set this bit to 1. 0 will reduce output power and degrade noise foor performance. ? for divide-by 4 or higher, it is recommended to set this bit to 0 to maintain fat output power across divider settings. setting this bit to 1, with divide-by 4 or higher provides higher output power compared to the divide- by 1 or two case. for example, to write 0_1111_1110 into vco_reg02h vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to reg 05h =0 _1111_1110, 0 010, 0 0 0 b. reg 05h [2:0] = 00; subsystem id 0 reg 05h [6:3] = 0010; vco register address 2d reg 05h [16:7] = 0 _1111_1110 ; divide by 62, max output rf gain, divider output stage gain = 0 3.4 vco_reg 03h confg bit type name width default description [0] wo fundamental/doubler mode selection 1 1 0- enable the frequency doubler mode of operation 1- enable fundamental mode of operation - for more information please see vco subsystem section. [1] wo reserved 1 0 reserved [2] wo manual rfo mode 1 0 0 - autorfo mode (recommended) 1 - manualrfo mode autorfo mode controls output buffers and rf divider enables according to rf divider setting in vco_reg 02h [5:0] manualrfo mode requires manual enables of individual blocks via vco_reg01h [4:3] wo rf buffer bias 2 0 program to 10b for output frequencies < 3000 mhz (when vco_reg03h[0] = 1) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 60 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz 3.4 vco_reg 03h confg bit type name width default description [8:5] wo spare 4 2 program to 00b for output frequencies > 3000 mhz, (when vco_reg03h[0] = 0) 3.5 vco_reg 04h cal/bias specifed performance is only guaranteed with the required settings in this table. other settings are not supported. bit type name width default description [2:0] wo vco bias 3 1 program to 1d [4:3] wo pll buffer bias 2 1 program to 0d [6:5] wo fndlmtr bias 2 2 program to 2d [8:7] wo preset cal 0 2 1 program to 1d 3.6 vco_reg05h cf_cal bit type name width default description [1:0] wo cf l 2 2 program to 0d [3:2] wo cf ml 2 2 program to 3d [5:4] wo cf mh 2 2 program to 2d [7:6] wo cf h 2 2 program to 0d [8] wo spare 1 0 program to 0d 3.7 vco_reg06h msb cal bit type name width default description [1:0] wo msb l 2 3 program to 3d [3:2] wo msb ml 2 3 program to 3d [5:4] wo msb mh 2 3 program to 3d [7:6] wo msb h 2 3 program to 3d [8] wo spare 1 0 dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with integrated vco - smt 61 HMC833LP6GE v01.1012 fractional-n pll with integrated vco 25 - 6000 mhz notes: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com

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